1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device and a method of manufacturing the same which can increase the capacitance of a capacitor by forming one or more trenches on top of a charge storage electrode.
2. Description of the Prior Art
Conventionally, as a semiconductor integrated circuit becomes highly integrated, a unit cell area is decreased. However, a minimum capacitance is needed to operate the device despite the reduction of the unit cell area. Accordingly, research to ensure the minimum required capacitance in a limited area is being undertaken.
FIG. 1 is a sectional view of a capacitor manufactured by a prior art technology.
An active region and a field region are defined by forming a field oxide film 2 on a silicon substrate 1. A gate oxide film 3 and a gate electrode 4 are formed on predetermined portions of the active region and the field region, and an insulation spacer 5 is formed on the side of the gate electrode 4. A source electrode 6A and a drain electrode 6B are formed on the portions of the silicon substrate 1 exposed to both sides of the gate electrode 4 by an impurity ion implantation process. An interlayer insulation film 7 is thickly formed on the entire structure including the MOSFET. Therefore, the MOSFET having a LDD structure is formed. A silicon nitride film 8 and a first polysilicon layer 9 are sequentially deposited on the interlayer insulation film 7. The exposed portions of the first polysilicon layer 9 and the silicon nitride film 8 are sequentially etched by an anisotropic etching process utilizing a contact hole mask. The anisotropic etching process is performed so that the interlayer insulation film 7 which is a lower layer is sufficiently exposed. A polysilicon is deposited on the surface of the first polysilicon layer 9 including a recess which is formed by etching the first polysilicon layer 9 and the silicon nitride film 8. The polysilicon is etched by an anisotropic etching process so that a part of the interlayer insulation film 7 constituting the bottom of the recess is exposed, thereby polysilicon spacers 10 are formed on the inner wall of the recess. A contact hole is formed by etching the exposed interlayer insulation film 7 by an anisotropic etching process utilizing the first polysilicon layer 9 and the polysilicon spacers 10 as an etching mask until a part of the source electrode 6A is exposed. The width of the contact hole can be smaller than when using the contact hole mask because the contact hole is formed by a self-alignment etching process, so that the high integration of the semiconductor integrated circuit is facilitated. A second polysilicon layer 11 is deposited on the first polysilicon layer 9 and the polysilicon spacers 10 including the contact hole.
The second and first polysilicon layers 11 and 9 are etched by an anisotropic etching process utilizing a charge storage electrode mask , therefore a charge storage electrode of a capacitor composed of the polysilicon spacers 10, the first polysilicon layer 9 and the second polysilicon layer 11 is formed. The charge storage electrode is of the same shape and size as the charge storage electrode mask.
A dielectric film 17 is formed on the surface of the charge storage electrode. A third polysilicon layer 18 is deposited on an exposed part of the silicon nitride film 8 including the dielectric film 17. Thereafter, the third polysilicon layer 18 is etched by an anisotropic etching process utilizing a plate electrode mask, a plate electrode composed of the third polysilicon layer 18 is formed finally.
There are limits of the prior art capacitor formed by the above-described process to ensuring the required capacitance for the operation of the device as the semiconductor integrated circuit becomes highly integrated